1. Field of the Invention
The present invention is related to a display device, and more particularly, to a display device having bi-directional shift registers.
2. Description of the Prior Art
Many techniques have been developed in order to improve poor viewing angle of large-size liquid crystal display (LCD) devices, such as multi-domain vertical alignment (MVA) and in-plane switching (IPS). For an LCD device which operates in MVA mode, color washout is a major drawback in display quality.
FIG. 1 is a diagram illustrating a prior art pixel 100 capable of improving color washout. As well-known to those skilled in the art, the pixels of an LCD device are arranged as a matrix. FIG. 1 depicts partial structure of the pixel 100, which includes a main gate line GL, a sub gate line GL′, a data line DL, a first thin film transistor switch T1, a second thin film transistor switch T2, a third thin film transistor switch T3, a first liquid crystal capacitor Clc1, a second liquid crystal capacitor Clc2, a first storage capacitor Cst1, a second storage capacitor Cst2, and a third storage capacitor Cst3. The first liquid crystal capacitor Clc1 and the first storage capacitor Cst1 are coupled to the drain of the first thin film transistor switch T1 (denoted by a node p1). The second liquid crystal capacitor Clc2 and the second storage capacitor Cst2 are coupled to the drain of the second thin film transistor switch T2 (denoted by a node p2). The third storage capacitor Cst3 is coupled to the drain of the third thin film transistor switch T3. The gates of the first thin film transistor switch T1 and the second thin film transistor switch T2 are coupled to the gate line GL, and the sources of the first thin film transistor switch T1 and the second thin film transistor switch T2 are coupled to the data line DL. The drain of the second thin film transistor switch T2 is coupled to the source of the third thin film transistor switch T3, and the gate of the third thin film transistor switch T3 is coupled to the sub gate line GL′. When the main gate line GL is at high level, the first thin film transistor switch T1 and the second thin film transistor switch T2 are both turned on for writing display voltages, and the nodes p1 and p2 are both at the level of the display voltages. Next, when the main gate line GL is lowered to low level and the sub gate line GL′ is raised to high level, the third thin film transistor switch T3 is turned on and charge sharing occurs between the third storage capacitor Cst3 and the display voltages which are stored in the first thin film transistor switch T1 and the second thin film transistor switch T2. Thus, a voltage difference established between the nodes p1 and p2 changes according to the third storage capacitor Cst3, thereby improving color washout.
On the other hand, in order to utilize larger panel area and reduce material costs, GOA (gate driver on array) technique has been developed in which the level shifters and shift registers of driving ICs are integrated in the substrate of the LCD panel. Although the pixel 100 in FIG. 1 is widely used in large-size LCD panels for improving color washout, it does not work with bi-directional shift registers.
FIG. 2 is a diagram illustrating a prior art bi-directional driving structure. For the first column of pixel units PX1-PXm each having the same structure as the pixel 100, two scan circuits are required for providing precharge and bi-directional scan: when the shift registers SR_1-SR_m performs forward-scan in a top-to-bottom sequence, the pixels are charged first and then perform precharge; when the shift registers SR_m-SR_1 performs reverse-scan in a bottom-to-top sequence, the pixels are charged after performing precharge. Therefore, the shift registers may not function correctly.